C8051F388-B Datasheet, PDF (183/285 Pages) Silicon Laboratories – Flash MCU Family

C8051F388/9/A/B
SFR Definition 21.11. SMB1DAT: SMBus Data
Bit
7
6
5
4
3
2
1
0
Name
SMB1DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xC2; SFR Page = F
Bit
Name
Function
7:0 SMB1DAT[7:0] SMBus1 Data.
The SMB1DAT register contains a byte of data to be transmitted on the SMBus1
serial interface or a byte that has just been received on the SMBus1 serial inter-
face. The CPU can read from or write to this register whenever the SI1 serial inter-
rupt flag (SMB1CN.0) is set to logic 1. The serial data in the register remains stable
as long as the SI1 flag is set. When the SI1 flag is not set, the system may be in the
process of shifting data in/out and the CPU should not attempt to access this regis-
ter.
Rev. 1.1
183