K4G323222A Datasheet, PDF (9/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
CMOS SGRAM
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1 CKEn CS RAS CAS WE DSF DQM BA
A8
A10,A9,
A7~A0
Note
Register
Refresh
Mode Register Set
H
Special Mode Register Set
Auto Refresh
H
Entry
Self
Refresh
Exit
L
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
Column
H
Address
Auto Precharge Enable
Write &
Auto Precharge Disable
Column
H
Address
Auto Precharge Enable
Block Write Auto Precharge Disable
&
H
Column
Auto Precharge Enable
Burst Stop
H
L
X LL LL
X
H
H
L L L HL X
L
LH HH
H
XX
HX XX
X L L HHL XV
X LH L HL XV
X LH L LL XV
X LH L LH XV
X LH HLL X
OP CODE
X
X
Row Address
L
Column
Address
H
(A0~A7)
L
Column
Address
H
(A0~A7)
L
Column
Address
H
(A0~A7)
X
1, 2
1,2,7
3
3
3
3
4,9
4
4, 6
4
4,6,9
4
4,6,9
7
Precharge
Bank Selection
Both Banks
Clock Suspend or
Active Power Down
Entry
Exit
Precharge Power Down
Mode
Entry
Exit
DQM
No Operation Command
H
X LL H
LH H
H
L
HX X
L
H XX X
LH H
H
L
HX X
LV V
L
H
HX X
H
X
LH H
H
X
HX X
Note : 1. OP Code : Operand Code
A0 ~ A10, BA : Program keys. (@MRS)
A6 : LCR select. (@SMRS)
Color register exists only one per DQi which both banks share.
Color is loaded into chip through DQ pin.
2. MRS can be issued only at both banks precharge state.
SMRS can be issued only if DQ′s are idle.
A new command can be issued at the next clock of MRS/SMRS.
V
L
LL X
X
X
H
H
XX
X
X
XX X
H
XX
X
X
VV
X
XX
V
X
8
H
XX
X
X
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Rev. 1.3 (Dec. 2000)
-9-