K4G323222A Datasheet, PDF (21/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
5. Write Interrupted by Precharge & DQM
CMOS SGRAM
CLK
CMD
WR
DQM
Note 2
PRE
Note 1
DQ
D0 D1 D2 D3
Masked by DQM
*Note : 1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of dual banks operation.
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
3) Read (BL=4)
WR
PRE
D0 D1 D2 D3
tRDL
Note 1,4
2) Block Write
CLK
CMD
DQ
BW
PRE
Pixel
tBPL
Note 1
CLK
CMD
RD
DQ(CL2)
DQ(CL3)
PRE
Note 2
Q0 Q1 Q2 Q3 ¹
Q0 Q1 Q2 Q3 ²
7. Auto Precharge
1) Normal Write (BL=4)
2) Block Write
CLK
CLK
CMD
WR
CMD
BW
DQ
3) Read (BL=4)
CLK
D0 D1 D2 D3
DQ
(CL 2, 3)
Note 3,4
Auto Precharge Starts
Pixel
tBPL
tRP
Note 3
Auto Precharge Starts
CMD
RD
DQ(CL2)
Q0 Q1 Q2 Q3
DQ(CL3)
Q0 Q1 Q2 Q3
Note 3
Auto Precharge Starts
*Note :1. tBPL : Block write data-in to PRE command delay
2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of other activated
bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
4. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
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