K4G323222A Datasheet, PDF (15/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
DEVICE OPERATIONS (Continued)
Entry to Power Down, Auto refresh, Self refresh and Mode reg-
ister Set etc. is possible only when both banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SGRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A8/AP. If
burst read or burst write command is issued with low on A8/AP,
the bank is left active until a new command is asserted. Once
auto precharge command is given, no new commands are pos-
sible to that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A8/AP after both banks have satisfied tRAS(min) require-
ment, performs precharge on both banks. At the end of tRP after
performing precharge all, both banks are in idle state.
AUTO REFRESH
The storage cells of SGRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,RAS
and CAS with high on CKE and WE. The auto refresh command
can only be asserted with both banks being in idle state and the
device is not in power down mode (CKE is high in the previous
cycle). The time required to complete the auto refresh operation
is specified by "tRC(min)". The minimum number of clock cycles
required can be calculated by driving "tRC" with clock cycle time
and them rounding up to the next higher integer. The auto
refresh command must be followed by NOP′s until the auto
refresh operation is completed. Both banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SGRAM is being used for nor-
mal data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 2048 auto refresh cycles once in
32ms.
CMOS SGRAM
SELF REFRESH
The self refresh is another refresh mode available in the
SGRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SGRAM. In self refresh
mode, the SGRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP′s
for a minimum time of "tRC" before the SGRAM reaches idle
state to begin normal operation. If the system uses burst auto
refresh during normal operation, it is recommended to use burst
2048 auto refresh cycles immediately after exiting self refresh.
DEFINE SPECIAL FUNCTION(DSF)
The DSF controls the graphic applications of SGRAM. If DSF is
tied to low, SGRAM functions as 512K x 32 x2 Bank SDRAM.
SGRAM can be used as an unified memory by the appropriate
DSF command. All the graphic function modes can be entered
only by setting DSF high when issuing commands which other-
wise would be normal SDRAM commands. SDRAM functions
such as Write, and WCBR change to SGRAM functions such as
Block Write and SWCBR respectively. See the section below for
the graphic functions that DSF controls.
SPECIAL MODE REGISTER SET(SMRS)
There is special mode registers in SGRAM. it is color register.
That usage will be explained in the "BLOCK WRITE" sections.
when A6 and DSF goes high in the same cycle as CS, RAS,
CAS and WE going low, Load Color Register(LCR) process is
executed and the color register is filled with color data for asso-
ciated DQ′s through the DQ pins. If A6 is high at SMRS, color
cycle is required to complete the write in the color register at
LCR. A new command can be issued in the next clock of LCR.
SMRS, compared with MRS, can be issued at the active state
under the condition that DQ′s are idle. As in write operation,
SMRS accepts the data needed through DQ pins. Therefore bus
contention must be avoided. The more detailed materials can be
obtained by referring corresponding timing diagram.
Rev. 1.3 (Dec. 2000)
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