K4G323222A Datasheet, PDF (45/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
Mode Register Set Cycle
CLOCK
CKE
0123456
HIGH
CS
RAS
*Note 2
CAS
*Note 1
ADDR
*Note 3
Key Ra
WE
DSF
DQM
DQ
Hi-Z
MRS New
Command
Auto Refresh Cycle
CMOS SGRAM
0 1 2 3 4 5 6 7 8 9 10
HIGH
tRC
Hi-Z
Auto Refresh
New Command
: Don′t care
* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS, RAS, CAS, & WE activation and DSF of low at the same clock cycle with address key will set internal
mode register.
2. Minimum 1 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Rev. 1.3 (Dec. 2000)
- 45