K4G323222A Datasheet, PDF (16/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
DEVICE OPERATIONS (Continued)
BLOCK WRITE
Block write is a feature allowing the simultaneous writing of
consecutive 8 columns of data within a RAM device during a sin-
gle access cycle. During block write the data to be written comes
from an internal "color" register and DQ I/O pins are used for
independent column selection. The block of column to be written
is aligned on 8 column boundaries and is defined by the column
address with the 3 LSB′s ignored. Write command with DSF=1
enables block write for the associated bank. A write command
with DSF=0 enables normal write for the associated bank. The
block width is 8 column where column="n" bits for by "n" part.
The color register is the same width as the data port of the
chip.It is written via a SWCBR where data present on the DQ pin
is to be coupled into the internal color register. The color register
provides the data masked by the DQ column select, and DQM
byte mask. Column data masking(Pixel masking) is provided on
an individual column basis for each byte of data. The column
mask is driven on the DQ pins during a block write command.
The DQ column mask function is segmented on a per bit
basis(i.e. DQ[0:7] provides the column mask for data bits[0:7],
DQ[8:15] provides the column mask for data bits[8:15], DQ0
masks column[0] for data bits[0:7], DQ9 masks column [1] for
data bits [8:15], etc). Block writes are always non-burst, inde-
pendent of the burst length that has been programmed into the
mode register. Back to back block writes are allowed provided
that the specified block write cycle time(tBWC) is satisfied. DQM
masking provides independent data byte masking during block
write exactly the same as it does during normal write operations,
except that the control is extended to the consecutive 8 columns
of the block write.
CMOS SGRAM
Timing Diagram to lllustrate tBWC
0
1
2
CLOCK
CKE
HIGH
CS
RAS
CAS
WE
DSF
1 CLK BW
Rev. 1.3 (Dec. 2000)
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