K4G323222A Datasheet, PDF (4/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
PIN CONFIGURATION (TOP VIEW)
CMOS SGRAM
DQ29 81
VSSQ 82
DQ30 83
DQ31 84
VSS 85
N.C 86
N.C 87
N.C 88
N.C 89
N.C 90
N.C 91
N.C 92
N.C 93
N.C 94
N.C 95
VDD 96
DQ0 97
DQ1 98
VSSQ 99
DQ2 100
100 Pin QFP
Forward Type
20 x 14 mm²
0.65mm pin Pitch
50 A7
49 A6
48 A5
47 A4
46 VSS
45 A10
44 N.C
43 N.C
42 N.C
41 N.C
40 N.C
39 N.C
38 N.C
37 N.C
36 N.C
35 VDD
34 A3
33 A2
32 A1
31 A0
*PQFP (Height = 3.0mmMAX)
TQFP (Height = 1.2mmMAX)
PIN CONFIGURATION DESCRIPTION
PIN
CLK
CS
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + tSS prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10
BA
RAS
CAS
WE
DQMi
DQi
DSF
VDD/VSS
VDDQ/VSSQ
N.C
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Define Special Function
Power Supply /Ground
Data Output Power /Ground
No Connection
Row / Column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and Row precharge.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.(Byte Masking)
Data inputs/outputs are multiplexed on the same pins.
block write and special mode register set.
Power Supply : +3.3V±0.3V/Ground
Provide isolated Power/Ground to DQs for improved noise immunity.
Rev. 1.3 (Dec. 2000)
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