K4G323222A Datasheet, PDF (48/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
FUNCTION TRUTH TABLE (TABLE 1, Continued)
ABBREVIATIONS
RA = Row Address(A0~A10)
NOP = No Operation Command
BA = Bank Address
CA = Column Address(A0~A7)
CMOS SGRAM
PA = Precharge All(A8)
AP = Auto Precharge(A8)
*Note : _{1. All entries assume that CKE was active(High) during the preceding clock cycle and the current clock cycle.}
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA(and PA).
5. Illegal if any banks is not idle.
6. Legal only if all banks are in idle or row active state.
FUNCTION TRUTH TABLE for CKE(TABLE 2)
Current
State
CKE CKE _{CS RAS CAS WE DSF}
n-1
n
ADDR
ACTION
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Exit Self Refresh --> ABI after tRC
Self
Refresh
L
H
L
H
H
H
X
L
H
L
H
H
L
X
L
H
L
H
L
X
X
X
Exit Self Refresh --> ABI after tRC
X
ILLEGAL
X
ILLEGAL
L
H
L
L
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Self Refresh)
H
X
X
X
X
X
X
X
INVALID
Both
L
H
H
X
X
X
X
Bank
L
H
L
H
H
H
X
Precharge
L
H
L
H
H
L
X
Power
Down
L
H
L
H
L
X
X
L
H
L
L
X
X
X
X
Exit Power Down --> ABI
X
Exit Power Down --> ABI
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
L
L
X
X
X
X
X
X
NOP(Maintain Power Down Mode)
H
H
X
X
X
X
X
X
Refer to Table 1
H
L
H
X
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
X
Enter Power Down
All
Banks
Idle
H
L
L
H
H
L
X
H
L
L
H
L
X
X
H
L
L
L
H
H
L
X
ILLEGAL
X
ILLEGAL
RA
Row (& Bank) Active
H
L
L
L
L
H
L
X
Enter Self Refresh
H
L
L
L
L
L
L
OP Code Mode Register Access
H
L
L
L
L
L
H
OP Code Special Mode Register Access
L
L
X
X
X
X
X
X
NOP
Any State
H
H
X
X
X
X
X
other than
H
L
X
X
X
X
X
Listed
Above
L
H
X
X
X
X
X
L
L
X
X
X
X
X
ABBREVIATIONS : ABI = All Banks Idle
X
Refer to Operations in Table 1
X
Begin Clock Suspend next cycle
X
Exit Clock Suspend next cycle
X
Maintain clock Suspend
*Note : _{7. After CKE′s low to high transition to exist self refresh mode. And a time of tRC(min) has to be elapse after CKE′s low to high}
transition to issue a new command.
8. CKE low to high transition is asynchronous as if restarts internal clock.
A minimum setup time "tSS + one clock" must be satisfied before any command other than exit.
9. Power-down and self refresh can be entered only from the all banks idle state.
10. Must be a legal command.
NOTE
7
7
8
8
9
9
9
10
10
Rev. 1.3 (Dec. 2000)
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