K4G323222A Datasheet, PDF (13/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SGRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock for proper
functionality and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SGRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When both banks
are in the idle state and CKE goes low synchronously with clock,
the SGRAM enters the power down mode from the next clock
cycle. The SGRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "tSS + 1CLOCK" before the high going
edge of the clock, then the SGRAM becomes active from the
same clock edge accepting all the input commands.
BANK SELECT (BA)
This SGRAM is organized as two independent banks of 524,288
words x 32 bits memory arrays. The BA inputs is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. When BA is asserted low, bank A is selected.
When BA is asserted high, bank B is selected. The bank select
BA is latched at bank activate, read, write mode register set and
precharge operations.
ADDRESS INPUT (A0 ~ A10)
The 19 address bits required to decode the 524,288 word loca-
tions are multiplexed into 11 address input pins(A0~A10). The 11
bit row address is latched along with RAS and BA during bank
activate command. The 8 bit column address is latched along
with CAS, WE and BA during read or write command.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SGRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin-
gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE, DSF and all the address inputs are ignored.
CMOS SGRAM
POWER-UP
SGRAMs must be powered up and initialized in a pre-
defined manner to prevent undefined operations.
1. Power must be applied to both CKE and DQM inputs to pull
them high and other pins are NOP condition at the inputs
before or along with VDD(and VDDQ) supply.
The clock signal must also be asserted at the same time.
2. After VDD reaches the desired voltage, a minimum pause of
200 microseconds is required with inputs in NOP condition.
3. Both banks must be precharged now.
4. Perform a minimum of 2 Auto refresh cycles to stabilize the
internal circuitry.
5. Perform a MODE REGISTER SET cycle to program the CAS
latency, burst length and burst type as the default value of
mode register is undefined.
At the end of one clock cycle from the mode register set cycle,
the device is ready for operation.
When the above sequence is used for Power-up, all the outputs
will be in high impedance state. The high impedance of outputs
is not guaranteed in any other power-up sequence.
cf.) Sequence of 4 & 5 may be changed.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SGRAM. It programs the CAS latency,
addressing mode, burst length, test mode and various vendor
specific options to make SGRAM useful for variety of different
applications. The default value of the mode register is not
defined, therefore the mode register must be written after power
up to operate the SGRAM. The mode register is written by
asserting low on CS, RAS, CAS, WE and DSF (The SGRAM
should be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0 ~ A10 and BA in
the same cycle as CS, RAS, CAS, WE and DSF going low is the
data written in the mode register. One clock cycle is required to
complete the write in the mode register. The mode register con-
tents can be changed using the same command and clock cycle
requirements during operation as long as both banks are in the
idle state. The mode register is divided into various fields
depending on functionality. The burst length field uses A0 ~ A2,
burst type uses A3, addressing mode uses A4 ~ A6, A7 ~ A8 , A10
and BA are used for vendor specific options or test mode. And
the write burst length is programmed using A9. A7 ~ A8 , A10 and
BA must be set to low for normal SGRAM operation. Refer to
table for specific codes for various burst length, addressing
modes and CAS latencies.
Rev. 1.3 (Dec. 2000)
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