K4G323222A Datasheet, PDF (29/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
Read & Write Cycle at Same Bank @Burst Length=4
CMOS SGRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
tRCD
*Note 1
tRC
HIGH
RAS
CAS
ADDR
Ra
Ca0
BA
*Note 2
Rb
Cb0
A8/AP
Ra
Rb
WE
DSF
DQM
DQ
(CL=2)
DQ
(CL=3)
tRAC
*Note 3
tRAC
*Note 3
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ ^{*Note 4}
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ ^{*Note 4}
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
*Note 5
tRDL
*Note 5
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] valid output data available after Row
enters precharge. Last valid output will be Hi-Z after tSHZ from the clcok.
3. Access time from Row address. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, & 8). At Full page bit burst, burst is wrap-around.
5. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Precharge
(A-Bank)
: Don′t care
Rev. 1.3 (Dec. 2000)
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