K4G323222A Datasheet, PDF (33/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
Page Read Cycle at Different Bank @Burst Length=4
CMOS SGRAM
CLOCK
CKE
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
*Note 1
HIGH
RAS
CAS
*Note 2
ADDR
RAa
CAa RBb
CBb
CAc
CBd
CAe
BA
A8/AP
RAa
RBb
WE
DSF
LOW
DQM
DQ
(CL=2)
DQ
(CL=3)
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read Precharge
(A-Bank) (A-Bank)
: Don′t care
*Note : 1. CS can be don′t care when RAS, CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Rev. 1.3 (Dec. 2000)
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