K4G323222A Datasheet, PDF (20/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(1) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
RD WR
D0 D1 D2 D3
RD
WR
Hi-Z _{D0 D1 D2 D3}
RD
WR
Hi-Z _D0
D1
D2
D3
RD
WR
Q0 ^Hi-Z D0 D1 D2 D3
Note 1
CMOS SGRAM
(2) CL=3, BL=4
CLK
i) CMD
DQM
RD WR
DQ
ii) CMD
DQM
D0 D1 D2 D3
RD
WR
DQ
iii) CMD
DQM
D0 D1 D2 D3
RD
WR
DQ
iv) CMD
RD
DQM
DQ
D0 D1 D2 D3
WR
Hi-Z _D0
D1
D2
D3
v) CMD
RD
DQM
DQ
WR
Hi-Z
Q0 _{Note 2} D0
D1
D2
D3
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
2. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
Rev. 1.3 (Dec. 2000)
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