K4G323222A Datasheet, PDF (8/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Symbol
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
-45
9
18
18
40.5
58.5
Version
-50
-7C
-60
10
15
12
15
15
18
15
15
18
40
45
42
100
55
60
60
CMOS SGRAM
Unit
-70
14
ns
20
ns
20
ns
49
ns
us
70
ns
2. Minimum delay is required to complete write.
3. This parameter means minimum CAS to CAS delay at block write cycle only.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
-45
-50
-7C
-60
-70
Symbol
Unit Note
Min Max Min Max Min Max Min Max Min Max
CAS Latency=3
4.5
5
-
6
7
CLK cycle time
tCC
1000
1000
1000
1000
1000 ns 1
CAS Latency=2
10
10
7.5
10
10
CLK to valid
output delay
CAS Latency=3
-
4
- 4.5 -
-
- 5.5 - 5.5
tSAC
ns 1, 2
CAS Latency=2
-
6
-
6
-
6
-
6
-
6
Output data hold time
tOH
2
-
2
-
2
-
2
-
2
- ns 2
CLK high pulse
width
CAS Latency=3
CAS Latency=2
tCH
1.75 -
3
-
2
3
-
-
-
2
- 2.5 -
-
3
-
3
3
-
ns 3
-
CLK low
pulse width
CAS Latency=3
1.75 -
2
-
-
- 2.5 -
3
-
CAS Latency=2
tCL
3
-
3
-
2
-
3
-
3
ns 3
-
CAS Latency=3
1.2 - 1.5 -
-
- 1.5 - 1.75 -
Input setup time
tSS
ns 3
CAS Latency=2
2.5 - 2.5 - 1.5 - 2.5 - 2.5 -
Input hold time
tSH
1
-
1
-
1
-
1
-
1
- ns 3
CLK to output in Low-Z
tSLZ
1
-
1
-
1
-
1
-
1
- ns 2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
CAS latency=2
-
-
4
6
- 4.5 -
-
6
-
-
6
- 5.5 - 5.5
ns -
-
6
-
6
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.3 (Dec. 2000)
-8-