K4G323222A Datasheet, PDF (30/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
Page Read & Write Cycle at Same Bank @Burst Length=4
CMOS SGRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
BA
A8/AP
tRCD
Ra
Ca0
Cb0
Ra
WE
*Note 2
*Note 2
Cc0
Cd0
tCDL
tRDL *Note 4
DSF
DQM
*Note 1
*Note 3
DQ
(CL=2)
DQ
(CL=3)
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
Qa0 Qa1 Qb0
Dc0 Dc1 Dd0 Dd1
Row Active
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
: Don′t care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. For -60/70 devices, tRDL can be programmed as 1CLK if Auto-Precharge is not used in the design
Rev. 1.3 (Dec. 2000)
- 30