K4G323222A Datasheet, PDF (7/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr/tf =1 / 1
1.4
See Fig. 2
3.3V
CMOS SGRAM
Unit
V
V
ns
V
Vtt = 1.4V
Output
•
870Ω
1200Ω
•
30pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
•
(Fig. 1) DC Output Load Circuit
Note : _{1. The VDD condition of K4G323222A-45/50/7C/60 is 3.135V~3.6V.}
Output
Z0=50Ω
50Ω
•
30pF
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
CAS Latency
CLK cycle time
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Symbol
CL
tCC(min)
tRRD(min)
tRCD(min)
tRP(min)
tRAS(min)
tRAS(max)
tRC(min)
-45
32
4.5 10
42
42
95
13 7
-50
32
5 10
32
32
85
11 7
Version
-7C
-
2
- 7.5
2
-
2
-
2
-
6
100
-
8
-60
32
6 10
32
32
75
10 7
-70
32
7 10
32
32
75
10 7
Unit
CLK
ns
CLK
CLK
CLK
CLK
us
CLK
Note
1
1
1
1
1
Last data in to row precharge
tRDL(min)
2
Last data in to new col.address delay tCDL(min)
1
Last data in to burst stop
tBDL(min)
1
Col. address to col. address delay
tCCD(min)
1
Block Write data-in to PRE command tBPL(min)
2
Block write cycle time
tBWC(min)
1
Mode Register Set cycle time
tMRS(min)
1
Number of valid output
CAS Latency=3
2
data
CAS Latency=2
1
CLK
2,5
CLK
2
CLK
2
CLK
CLK
CLK
3
CLK
ea
4
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
Rev. 1.3 (Dec. 2000)
-7-