K4G323222A Datasheet, PDF (17/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
CMOS SGRAM
SUMMARY OF 4M Byte SGRAM BASIC FEATURES AND BENEFITS
Features
Interface
512K x 32 x 2 SGRAM
Synchronous
Benefits
Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Bank
2 ea
Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.
Page Depth / 1 Row
Total Page Depth
Burst Length(Read)
256 bit
2048 bytes
1, 2, 4, 8 Full Page
High speed vertical and horizontal drawing.
High speed vertical and horizontal drawing.
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
Burst Length(Write)
Burst Type
CAS Latency
Block Write
1, 2, 4, 8 Full Page
BRSW
Sequential & Interleave
2, 3
8 Columns
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
Switch to burst length of 1 at write without MRS.
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.
Color Register
Mask function
1 ea.
DQM0-3
Pixel Mask at Block Write
A and B bank share.
Byte masking(pixel masking for 8bpp system) for data-out/in
Byte masking(pixel masking for 8bpp system) for color by DQi
Rev. 1.3 (Dec. 2000)
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