K4G323222A Datasheet, PDF (41/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
Burst Read Single bit Write Cycle @Burst Length=2, BRSW
CMOS SGRAM
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
*Note 1
HIGH
CS
RAS
CAS
ADDR
RAa
BA
A8/AP
RAa
CAa RBb CAb
RBb
*Note 2
RAc CBc
CAd
RAc
WE
DSF
DQMi
DQ
(CL=2)
DQ
(CL=3)
Row Active
(A-Bank)
DAa0
DAa0
QAb0 QAb1
DBc0
QAb0 QAb1
DBc0
QAd0 QAd1
QAd0 QAd1
Row Active
(B-Bank)
Write
(A-Bank) _{Read with}
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Precharge
(A-Bank)
: Don′t care
*Note : 1. BRSW mode is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Rev. 1.3 (Dec. 2000)
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