K4G323222A Datasheet, PDF (5/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
CMOS SGRAM
ABSOLUTE MAXIMUM RATINGS(Voltage referenced to VSS)
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Unit
V
V
°C
W
mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD, VDDQ
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDDQ+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
-
-
V
Output low voltage
VOL
-
-
0.4
V
Input leakage current
ILI
-10
-
10
uA
Output leakage current
ILO
-10
-
10
uA
Output Loading Condition
see figure 1
Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDD.
5. The VDD condition of K4G323222A-45/50/7C/60 is 3.135V~3.6V.
Note
5
1
2
IOH = -2mA
IOL = 2mA
3
4
CAPACITANCE (VDD/VDDQ = 3.3V, TA = 23°C, f = 1MHz)
Pin
Symbol
Min
Clock
CCLK
-
RAS, CAS, WE, CS, CKE, DQMi,DSF
CIN
-
Address
CADD
-
DQi
COUT
-
Max
4.0
4.0
4.0
5.0
Unit
pF
pF
pF
pF
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between VDD and VSS
Decoupling Capacitance between VDDQ and VSSQ
Symbol
CDC1
CDC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note : 1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
-5-
Rev. 1.3 (Dec. 2000)