K4G323222A Datasheet, PDF (11/49 Pages) Samsung semiconductor – 32Mbit SGRAM

K4G323222A
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA
A10
RFU
(Note 1)
A9
W.B.L
(Note 2)
A8
A7
TM
A6
A5
A4
CAS Latency
CMOS SGRAM
A3
A2
A1
A0
BT
Burst Length
Test Mode
CAS Latency
A8 A7
Type
A6 A5 A4 Latency
0 0 Mode Register Set 0 0 0 Reserved
01
Vendor
001
-
10
11
Use
Only
010
2
011
3
Write Burst Length
1 0 0 Reserved
A9
Length
1 0 1 Reserved
0
Burst
1 1 0 Reserved
1
Single Bit
1 1 1 Reserved
Burst Type
A3
Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0
BT=0
000
1
001
2
010
4
011
8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 256(Full)
BT=1
Reserved
Reserved
4
8
Reserved
Reserved
Reserved
Reserved
(Note 3)
Special Mode Register Programmed with SMRS
Address
BA
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Function
X
LC
0
X
Load Color
A6
Function
0
Disable
1
Enable
POWER UP SEQUENCE
SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 may be changed.
The device is now ready for normal operation.
Note : 1. RFU(Reserved for Future Use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
3. The full column burst(256bit) is available only at Sequential mode of burst type.
Rev. 1.3 (Dec. 2000)
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