7220 Datasheet, PDF (87/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.8 Multi-master I²C-BUS interface
(4) Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit
addressing format. The respective address communication formats is described below.
Π7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I²C control register (address
00DA16) to “0.” The first 7-bit address data transmitted from the master is compared with the high-
order 7-bit slave address stored in the I²C address register (address 00D816). At the time of this
comparison, address comparison of the RBW bit of the I²C address register (address 00D816) is not
made. For the data transmission format when the 7-bit addressing format is selected, refer to
“Figure 2.8.12, (1) and (2).”
 10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the I²C control register (address
00DA16) to “1.” An address comparison is made between the first-byte address data transmitted
from the master and the 7-bit slave address stored in the I²C address register (address 00D816).
At the time of this comparison, an address comparison between the RBW bit of the I2C address
__
register
(address
00D816)
and
the
R/W
bit
which
is
the
last bit
__
of
the
address
data
transmitted
from
the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control data but also is processed as an
address data bit.
When the first-byte address data matches the slave address, the AAS bit of the I²C status register
(address 00D916) is set to “1.” After the second-byte address data is stored into the I²C data shift
register (address 00D716), make an address comparison between the second-byte data and the
slave address by software. When the address data of the 2nd byte matches the slave address, set
the
RBW
bit
of
the
I²C
address
register (address
__
00D816)
to
“1”
by
software.
This
processing
can
match the 7-bit slave address and R/W data, which are received after a RESTART condition is
detected, with the value of the I²C address register (address 00D816). For the data transmission
format when the 10-bit addressing format is selected, refer to “Figure 2.8.12, (3) and (4).”
S Slave address R/W A Data A Data A/A P
7 bits
“0”
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S Slave address R/W A Data A Data A P
7 bits
“1”
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Data
A
Data A/A P
7 bits
“0”
8 bits
1 to 8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
S
Slave address
1st 7 bits
R/W
A
Slave address
2nd byte
A
Sr
Slave address
1st 7 bits
R/W
Data
A
Data
A
P
7 bits
“0”
8 bits
7 bits
“1” 1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
1 to 8 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W: Read/Write bit
Fig. 2.8.12 Address data communication format
From master to slave
From slave to master
2-60
7220 Group User’s Manual