7220 Datasheet, PDF (77/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.8 Multi-master I²C-BUS interface
(2) I²C address register (S0D: address 00D816)
The I²C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In
the addressing mode, the slave address written in this register is compared with the address data
to be received immediately after the START condition are detected.
s Bit 0: Read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode,
the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the
I²C address register.
The RBW bit is cleared to “0” automatically when the stop condition is detected.
s Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing
mode, the address data transmitted from the master is compared with the contents of these bits.
Figure 2.8.3 shows the I²C address register.
I²C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I²C address register (S0D) [Address 00D816]
B
Name
0 _{Read/write bit}
(RBW)
1 _{Slave address}
to
7
(SAD0 to SAD6)
Functions
After reset R W
0: Read
1: Write
0 _RW
The address data transmitted from
the master is compared with the
contents of these bits.
0 _RW
Fig. 2.8.3 I²C address register
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7220 Group User’s Manual