7220 Datasheet, PDF (185/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.1 Example of multi-line display
(4) VSYNC interrupt processing routine when setting multiple interrupts
Figure 5.1.11 shows the flowchart of VSYNC interrupt processing routine when setting multiple interrupts.
A’ and B’ are the setting routines for multiple interrupts.
A’
Set routine for
multiple
interrupts
Enable state of
multiple interrupts
(Timer 1)
ICON1, ICON2: Interrupt control registers 1, 2
V_ICON1, V_ICON2 : Back up RAM for interrupt control
registers 1, 2 during V SYNC interrupt
VSYNC interrupt processing routine
A : Accumulator
X : Index register X
Y : Index register Y
T
←“0”
D
←“0”
T : X modified operation mode flag
D : Decimal operation mode flag
V_ICON1
←ICON1
V_ICON2
←ICON2
ICON1 (address 00FE 16)←“000000012”
ICON2 (address 00FF 16)←“000000002”
I
←“0”
Push registers X, Y, A
VSYNC interrupt processing
←Enable Timer 1 interrupt to
take priority than V SYNC interrupt.
And also, be sure to disable the following interrupts:
-VSYNC interrupt
-all interrupts with lower priority than V SYNC
interrupt.
Pop the registers X, Y, A
B’
Disable
multiple interrupts
I
ICON1
ICON2
←“1”
←V_ICON1
←V_ICON2
RETURN
←Disable all interrupts
←Pop ICON 1 and 2 contents
during VSYNC interrupt
Fig. 5.1.11 Flowchart of VSYNC interrupt processing routine (when setting multiple interrupts)
5-12
7220 Group User’s Manual