7220 Datasheet, PDF (182/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.1 Example of multi-line display
5.1.7 Set of multiple interrupts
(1) When not setting multiple interrupts
When two or more interrupt requests occur at the same sampling point, the interrupt with the higher
priority (refer to “2.5 Interrupts, Table 2.5.1”) is received. This priority level is determined by
hardware but various priority processing by software can be executed using the interrupt enable bit
and each interrupt disable flag (I).
Assume, for example, that all interrupts (CRT, V , SYNC Timer 1) are enabled. When the multiple
interrupt is not set, these interrupt request bits are set to “1” and the interrupts are determined by
hardware as follows:
ŒCRT interrupt
VSYNC interrupt
ŽTimer 1 interrupt
Figure 5.1.8 shows the timing of interrupt processing when not setting multiple interrupts.
The I flag is set to “1” (all interrupts are disabled) automatically by hardware as soon as the interrupt
processing starts. Unless the I flag is cleared to “0,” other interrupt will not occur during the interrupt
processing.
CRT interrupt request bit ¹
0
1
VSYNC interrupt request bit
0
1
Timer 1 interrupt request bit
0
CRT interrupt processing
1
VSYNC interrupt processing
2
Timer 1 interrupt processing
3
3’
Interrupt disable flag (I)
Fig. 5.1.8 Timing of interrupt processing when not setting multiple interrupts
7220 Group User’s Manual
5-9