7220 Datasheet, PDF (196/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.4 Example of I²C-BUS interface control (M37221Mx-XXXSP/FP)
5.4.4 General flowchart
The processing routines which controls I²C-BUS devices branch to the write processing routine and the
read processing routine. The data output processing routine is used as the common processing routine.
(1) Write processing routine
Œ

Ž


Slave address ^A
A
A
S _{(W) “A016”}
C Sub-address C
K
K
Data
CP
K
A: Accumulator
S1: I²C status register
S2: I²C clock control register
S1D: I²C control register
IICE: Multi-master I ²C interface interrupt
enable bit
BB: Bit 5 of I²C status register
Write start
Initialization
S2 (address 00DB 16)
S1D (address 00DA 16)
IICE (bit6 at address 00FE 16)
S1 (address 00D9 16)
“11000101 2”
“01001000 2”
“0”
“00010000 2”
Disable multi-master I ²C-BUS interface interrupt.
Setting for outputting the START condition
in data output processing routine.
A Slave address (W) “A0 16”
Data output
Within 10
machine
cycles
I
S1 (address 00F8 16)
S1 (address 00F8 16)
I
End
“1”
“11000000 2”
“11010000 2”
“0”
Œ Transmit the START condition and slave address (W).
Ž Transmit sub-address and data.
Note 1: Refer to “(3) Data output processing
routine.”
 _{Transmit the STOP condition.}
Note 2: Be sure to set between S1 and S1 within
10 machine cycles.
Fig. 5.4.4 Flowchart of write processing routine
7220 Group User’s Manual
5-23