7220 Datasheet, PDF (267/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPENDIX
6.7 Control registers
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 1 0 0 CPU mode register (CPUM) (CM) [Address 00FB16]
B
Name
0, 1 Fix these bits to “0.”
Functions
2 Stack page selection ^{0: 0 page} (Note)
bit (CM2)
1: 1 page
3 Fix these bits to “1.”
to
5
6, 7
Note: This bit is set to “1” after reset release.
After reset R W
0
RW
1
RW
1
RW
Indeterminate R W
Fig. 6.7.27 CPU mode register
Address 00FB16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC16]
B
Name
Functions
After reset R W
0 Timer 1 interrupt
0 : No interrupt request issued
request bit (TM1R) 1 : Interrupt request issued
1 Timer 2 interrupt
0 : No interrupt request issued
request bit (TM2R) 1 : Interrupt request issued
2 Timer 3 interrupt
0 : No interrupt request issued
request bit (TM3R) 1 : Interrupt request issued
3 Timer 4 interrupt
0 : No interrupt request issued
request bit (TM4R) 1 : Interrupt request issued
4 CRT interrupt
0 : No interrupt request issued
request bit (CRTR) 1 : Interrupt request issued
5 VSYNC interrupt
0 : No interrupt request issued
request bit (VSCR) 1 : Interrupt request issued
6 ^{Multi-master I2C-BUS interface} 0 : No interrupt request issued
interrupt request bit (IICR) _{1 : Interrupt request issued}
7 INT3 interrupt
request bit (IT3R)
0 : No interrupt request issued
1 : Interrupt request issued
0 RV
0 RV
0 RV
0 RV
0 RV
0 RV
0 RV
0 RV
(See note)
V: “0” can be set by software, but “1” cannot be set.
Note : M37220M3-XXXSP/FP
6 Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
0 R—
Fig. 6.7.28 Interrupt request register 1
Address 00FC16
6-48
7220 Group User’s Manual