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7220 Datasheet, PDF (83/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER | |||
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FUNCTIONAL DESCRIPTION
2.8 Multi-master I2C-BUS interface
s Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of
the PIN bit changes from â1â to â0.â At the same time, an interrupt request signal is sent to the
CPU. The PIN bit is set to â0â in synchronization with a falling edge of the last clock (including the
ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a
falling edge of the PIN bit. When the PIN bit is â0,â the SCL is kept in the â0â state and clock
generation is disabled. Figure 2.8.7 shows an interrupt request signal generating timing chart.
The PIN bit is set to â1â in any one of the following conditions.
⢠Executing a write instruction to the I2C data shift register (address 00D716).
⢠When the ESO bit is â0â
⢠At reset
The conditions in which the PIN bit is set to â0â are shown below:
⢠Immediately after completion of 1-byte data transmission (including when arbitration lost is detected)
⢠Immediately after completion of 1-byte data reception
⢠In the slave reception mode, with ALS = â0â and immediately after completion of slave address
or general call address reception
⢠In the slave reception mode, with ALS = â1â and immediately after completion of address data
reception
s Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to â0,â this bus system
is not busy and a START condition can be generated. When this bit is set to â1,â this bus system
is busy and the occurrence of a START condition is disabled by the START condition duplication
prevention function (Note).
This flag can be written by software only in the master transmission mode. In the other modes, this
bit is set to â1â by detecting a START condition and set to â0â by detecting a STOP condition. When
the ESO bit of the I2C control register (address 00DA16) is â0â and at reset, the BB flag is kept in
the â0â state.
s Bit 6: Communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is â0,â the reception
mode is selected and the data of a transmitting device is received. When the bit is â1,â the
transmission mode is selected and address data and control data are output into the SDA in
synchronization with the clock generated on the SCL.
When the ALS bit of the I2C control register (address 00F916) is â0â in the slave reception mode
is selected, the TRX bit is set to â1â (transmit) if the least significant bit (R/W bit) of the address
data transmitted by the master is â1.â When the ALS bit is â0â and the R/W bit is â0,â the TRX bit
is cleared to â0â (receive).
The TRX bit is cleared to â0â in one of the following conditions.
⢠When arbitration lost is detected.
⢠When a STOP condition is detected.
⢠When occurrence of a START condition is disabled by the START condition duplication prevention
function (Note).
⢠With MST = â0â and when a START condition is detected.
⢠With MST = â0â and when ACK non-return is detected.
⢠At reset
2-56
7220 Group Userâs Manual
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