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7220 Datasheet, PDF (70/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER | |||
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FUNCTIONAL DESCRIPTION
2.7 Serial I/O
2.7.5 Serial I/O data receive method (when an internal clock is selected)
(1) Initialization
First, set the serial I/O mode register (address 00DC16) as follows.
 Select the synchronous clock (SM2 = â1,â SM1, SM0).
 Set P20 as pin SCLK (SM3 = â1â). Pin P21/SOUT is not used when receiving serial data. However,
since the serial I/O port selection bit (SM3) is also used for setting pin SOUT, port P21 is automatically
set as pin SOUT and loses its general-purpose I/O port function.
 Select the serial input pin by the serial input pin selection bit (SM6). When SM6 = â0,â signal is
input from pin P22/SIN; when SM6 = â1,â signal is input from pin P21/SOUT. When pin P22/SIN is a
input pin, set the port P2 direction register to input mode (â0â). For pins P20/SCLK and P21/SOUT, the
corresponding bits of the port P2 direction register are automatically set by setting the serial I/O
mode register.
(2) Receive enable state
After the above setting have been made, write âFF16â to the serial I/O register (address 00DD16). The
serial I/O counter is then set to â0716â during the write cycle and receive is enabled.
(3) Receive operation
The data from the serial I/O data input pins (SOUT or SIN) is received one bit at a time into the serial
I/O register in synchronization with rising edges of the transfer clock.
Receive operation is performed according to bit 5 (SM5) of the serial I/O mode register:
 When SM5 is set to â0,â data is received from MSB (bit 7) of the register and shifted to the right
(to low-order bit) every time new data is received.
 When SM5 is set to â1,â data is received from LSB (bit 0) of the register and shifted to the left (to
high-order bit) every time new data is received.
When all 8-bit data have been received, the serial I/O interrupt request bit (bit 2) of the interrupt
request register 2 (address 00FD16) is set to â1.â
MSB
LSB
When receiving
D0
D1 D0
Transfer clock
D2 D1 D0
â¢
â¢
â¢
D7 D6 D5 D4 D3 D2 D1 D0
Serial I/O register
Note: To start receiving, set âFF16â to the serial I/O register.
Fig. 2.7.4 Serial I/O register when receiving (when SM5 = â0â)
7220 Group Userâs Manual
2-43
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