7220 Datasheet, PDF (75/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.8 Multi-master I²C-BUS interface
Serial
data
(SDA)
Noise
elimination
circuit
b7
I²C address register
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
S0D
Address comparator
Data
control
b7
circuit
b0
I ²C data shift register
S0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
b0
AL AAS AD0 LRB
MST TRX BB PIN
AL
circuit
BB
circuit
S1
Internal data bus
I² C status
register
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
b0
b7
b0
ACK
ACK
BIT
FAST
MODE
CCR4
CCR3
CCR2
CCR1
CCR0
BSEL1
BSEL0
10BIT
SAD
ALS
ESO BC2 BC1 BC0
S2
I²C clock control register
S1D I²C control register
Clock division
System clock (φ)
Bit counter
Fig. 2.8.1 Block diagram of multi-masteer I²C-BUS interface
2.8.1 Construction of multi-master I²C-BUS interface
The multi-master I²C-BUS interface consists of the following :
q I²C address register
q I²C data shift register
q I²C clock control register
q I²C control register
q I²C status register
q Other control circuits
The data transfer with the internal CPU is performed via data bus, the data transfer with an external device
is performed via ports P11–P14. When using multi-master I²C-BUS interface, these ports P11–P14 are
assigned to the following functions.
q P11: Multi-master I²C-BUS interface Synchronous clock input/output pin 1 (SCL1)
q P12: Multi-master I²C-BUS interface Synchronous clock input/output pin 2 (SCL2)
q P13: Multi-master I²C-BUS interface data input/output pin 1 (SDA1)
q P14: Multi-master I²C-BUS interface data input/output pin 2 (SDA2)
The shift clock to determine the transfer speed of serial data is selected by the I²C clock control register
(refer to “Figure 2.8.4”).
A serial data and a serial clock is referred as “SDA,” “SCL” respectively, hereafter.
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7220 Group User’s Manual