7220 Datasheet, PDF (101/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.11 CRT display function
2.11.1 Display position
The display positions of characters are specified in units called a “block”. There are 2 blocks, block 1 and
block 2. Up to 24 characters can be displayed in 1 block (refer to “2.11.3 Memory for display”).
The display position of each block in both horizontal and vertical directions can be set by software.
The horizontal direction is common to all blocks, and is selected from 64-step display positions in units of
4 TC (TC = oscillation cycle for display).
The display position in the vertical direction is selected from 128-step display positions for each block in
units of 4 scanning lines. The display position in the vertical direction is determined by counting the
horizontal sync signal (HSYNC).
At this time, it starts to count the rising edge (falling edge^V) of HSYNC signal from after about 1 machine cycle
of rising edge (falling edge^V) of VSYNC signal. So interval from rising edge (falling edge^V) of HSYNC signal
needs enough time (2 machine cycles or more) for avoiding jitter.
V:The polarity of HSYNC and VSYNC signals can select by the CRT port control register (address 00EC16).
When clearing corresponding bits to “0,” positive polarity is selected, when setting to “1,” negative
polarity is selected. Refer to “2.11.7 CRT output pin control” for detail.
VSYNC signal input
8 machine cycles or more (See note 4)
VSYNC control signal
in microcomputer
Period of counting
HSYNC signal
0.125 µs to 0.25 µs (See note 2)
(See note 3)
HSYNC signal input
8 machine cycles or more
(See note 4)
↑
↑
↑
↑
↑
↑
Not count 1
2
3
4
5
When bits 0 and 1 of the CRT port control register (address 00EC16)
are set to “1” (negative polarity)
Note 1: The vertical position is determined by counting falling
edge of HSYNC signal after rising edge of VSYNC control
signal in the microcomputer.
2: At f(XIN) = 8 MHz
3: Do not generate falling edge of HSYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
4: Pulse width of VSYNC and of HSYNC signals needs 8 machine
cycles or more.
Fig. 2.11.4 Count method of synchronous signal
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7220 Group User’s Manual