7220 Datasheet, PDF (74/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.8 Multi-master I²C-BUS interface
2.8 Multi-master I²C-BUS interface
The multi-master I²C-BUS interface is a serial communications circuit, conforming to the Philips I²C-BUS
data transfer format. This interface, offering both an arbitration lost detection and a synchronous functions,
is useful for the multi-master serial communications.
Figure 2.8.1 shows a block diagram of the multi-master I²C-BUS interface and Table 2.8.1 shows multi-
master I²C-BUS interface functions.
The M37220M3-XXSP/FP does not have this function.
Table 2.8.1 Multi-master I²C-BUS interface functions
Item
Function
In conformity with Philips I²C-BUS standard:
10-bit addressing format
Format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I²C-BUS standard:
Communication mode
Master transmission
Master reception
Slave transmission
Slave reception
SCL clock frequency
16.1 kHz to 400 kHz (at f = 4 MHz)
f: System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of patent rights or other rights attributable
to the use of the control function (bits 6 and 7 of the I²C control register at address 00DA16) for
connections between the I²C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
7220 Group User’s Manual
2-47