7220 Datasheet, PDF (177/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.1 Example of multi-line display
(2) VSYNC interrupt processing routine
The VSYNC interrupt processing routine consists of; multi-line display start processing and multi-line
display correction processing. The correction processing corrects erroneous multi-line display due to
various influences.
Setting for
multiple
interrupts
ICON1, ICON2: Interrupt control registers 1, 2
CC : CRT control register
CRTE : Bit 4 of interrupt control register 1
Line counter : Counter RAM for line counting
<CRT interrupt enable bit>
F_VSYNC : VSYNC flag
CRTR : Bit 4 of interrupt request register 1
CV1,CV2 : Vertical position registers 1, 2
<CRT interrupt request bit>
V_ICON1, V_ICON2 : Back up RAM for interrupt control
registers 1, 2 during V SYNC interrupt
A : Accumulator
VSYNC interrupt processing routine
X : Index register X
Y : Index register Y
T : X modified operation mode flag
T
←“0”
D : Decimal operation mode flag
D
←“0”
V_ICON1
←ICON1
←Push ICON1 contents during V SYNC interrupt
V_ICON2
←ICON2
←Push ICON2 contents during V SYNC interrupt
ICON1 (address 00FE 16) ←“000000012” Œ ←Enable only Timer 1 interrupt
ICON2 (address 00FF 16) ←“000000002” 
I
←“0”
←Enable multipule interrupt set by steps Œ, 
Push registers X, Y, A
(Refer to “5.1.7 (2)”)
F_VSYNC
=0
=1
Pass this
process only
once at
display start.
F_VSYNC
←“0”
CRTR (bit 4 at address 00FE 16)←“0”
CRTE (bit 4 at address 00FC 16)←“1”
CC (address 00EA16)
←“0716”
←Enable CRT interrupt
←All blocks display on
C
Correction for
erroneous
multi-line display
(Refer to “5.1.6”)
Line counter←“2”
CV1←Vertical display start position of the 1st line (block 1)
CV2←Vertical display start position of the 2nd line (block 2)
CRTR (bit 4 at address 00FE 16)←“0”
Setting for
multiple
interrupts
Pop registers X, Y, A
I
←“1”
ICON1
←V_ICON1
ICON2
←V_ICON2
←Disable all interrupts
←Pop ICON 1 and 2 contents during
VSYNC interrupt (Refer to “5.1.7 (2)”)
RETURN
Note: The multiple interrupt priority of this system
interrupt is as below.
Timer 1 > VSYNC > CRT
Fig. 5.1.4 Flowchart of VSYNC interrupt processing routine
5-4
7220 Group User’s Manual