7220 Datasheet, PDF (33/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.1 Central processing unit
2.1.4 Program counter (PC)
The program counter is a 16-bit counter consists of PCH and PCL, both of which are 8-bit registers.
The program counter indicates the address of the program to be executed next.
The M37221M6-XXXSP/FP uses the stored program system. To start a new operation, transfer the instruction
and the data, from the memory to the CPU. Ordinary, the program counter is controlled to indicate the
memory address to be sent next. After each instruction is executed, the instruction required next is called
out and this cycle is repeated until finished.
Note: The program counter of the M37221M6-XXXSP/FP is controlled automatically; however, make sure
to avoid differences between program flow and the program counter contents when operating the
stack pointer or directly changing the program counter contents.
2.1.5 Processor status register (PS)
The processor status register is an 8-bit register. It consists of 5 flags, which indicate the state after
arithmetic operations related to the internal CPU, and 3 flags which determine operation.
The following explains each of these flags. Refer to “6.9 Machine instruction table” of this USER’S
MANUAL or “SERIES 740 <SOFTWARE> USER’S MANUAL” concerning the change of these flags.
(1) Carry flag (C) ...................................................... Bit 0
This flag stores any carry or borrow from the ALU after an arithmetic operation and is also changed
by the Shift instruction or Rotate instruction.
This flag is set to “1” by using the SEC instruction and is cleared to “0” by using the CLC instruction.
(2) Zero flag (Z) ........................................................ Bit 1
This flag is set to “1” when the result of an arithmetic operation or a data transfer is “0” and is cleared
to “0” by any other result.
This flag has no meaning in the decimal mode.
(3) Interrupt disable flag (I) ................................... Bit 2
This flag disables interrupts. When this flag is “1,” all interrupts except the BRK interrupt and reset
are disabled. This flag immediately becomes “1” when an interrupt is received. This flag is set to “1”
by using the SEI instruction and is cleared to “0” by using the CLI instruction.
(4) Decimal operation mode flag (D) ................... Bit 3
This flag determines whether addition and substruction are performed in binary or decimal notation.
Binary arithmetic is performed when this flag is “0” and decimal arithmetic is performed with treating
each word as a 2-digit decimal when this flag is “1.” Decimal adjust is performed automatically at this
time. This flag is set to “1” by using the SED instruction and is cleared to “0” by using the CLD
instruction. Only the ADC and SBC instructions are used for decimal arithmetic.
Since this flag directly affects calculations, always initialize it after a reset.
(5) Break flag (B) ...................................................... Bit 4
This flag determines whether or not an interrupt occurred by using the BRK instruction. When a BRK
instruction interrupt occurs, the flag B is set to “1”; for all other interrupts the flag is set to “0” and
pushed to the stack.
For the M37221M6-XXXSP/FP, interrupt vectors by using the BRK instruction are independent of
other interrupts, and it is possible to determine the cause of interrupt by jumping to the vector
address inherent to each interrupt. Therefore, it is not specifically necessary to refer to this flag.
Note: The BRK instruction will be used for debugging.
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7220 Group User’s Manual