7220 Datasheet, PDF (198/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.4 Example of I²C-BUS interface control (M37221Mx-XXXSP/FP)
(3) Data output processing routine
The data output processing routine is the common routine within the transmit/receive processing
routine.
Data output
Store the number of output bytes to internal RAM
S0 (address 00D7 16)←Data to be output
A: Accumulator
S0: I²C data shift register
S1: I²C status register
TRX: Communication mode specification bit
AL: Arbitration lost detecting flag
PIN: Multi-master I²C interface interrupt
enable bit
LRB: Last receive bit
N
The first byte ?
Yes
S1 (address 00D9 16)←111100002
Output A.
Preparation for judging timeout.
An error
such as timeout occurs ?
TRX (bit 6 at address 00D9 16)≠“0” or
AL (bit 3 at address 00D9 16)≠“1” ?
An error occurs when data
transmit does not end within a
certain period.
TRX = 0 : arbitration lost is
AL = 1 : detected (error)
Error
No error
= 1 (Not yet)
1-byte data transmit completes?
PIN (bit 4 at address 00D9 16) ≠ “1” ?
= 0 (Completion of 1-byte data transmit)
Stop judging of timeout.
LRB (bit 0 at address 00D9 16) ≠ “1” ?
= 0 (ACK)
Store the next data to A
= 1 (No ACK)
No ACK?
No
The last byte ?
Yes
END
Fig. 5.4.6 Flowchart of data output processing routine
END
7220 Group User’s Manual
5-25