7220 Datasheet, PDF (189/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP)
(2) Correction example 2
The loop processing is performed between  and Ž in Figure 5.3.3. Two examples of this part are
shown in detail. Example A corrects in loop units and example B corrects only error instructions.
Examples A and B are the same operation, differing in processing time and correction bytes only.
Depending on the contents of loop processing, it may be preferable to include correct codes with the
codes to be corrected, simplifying the correction program and making it easier to read.
When omitting FE96H () and correcting from FE98H, the program cannot move to FE96H by the
BPL instruction (the jump destination addresses of the BPL instruction are limited to bytes between
–128 and +127). Therefore, the example B is provided.
Program before correction
Address
Machine
Description style
instructions
FE96
9525
STA 025H, X 
FE98
FE99
CA
10FB
DEX
BPL 0FE96H Ž
(See note 2)
FE9B
60
RTS
Example A
Address
(block 2)
02E0
02E2
02E5
02E6
02E7
02E9
Correction program
Machine
Description style
instructions
9525
STA 025H, X 
9D2501
STA 0125H, X
3A
INC A
CA
10F7
DEX
BPL 02E0H 
(See note 2)
60
RTS (See note 1)
Example B
Address
(block 2)
02E0
02E3
02E4
02E5
02E7
02EA
Correction program
Machine
Description style
instructions
9D2501
STA 0125H, X
3A
INC A
CA
DEX
3003
BMI 02EAH
(See note 2)
4C96FE
4C9BFE
JMP FE96H
JMP FE9BH Œ
(See note 1)
Notes 1: In Œ, FE9BH is specified as the return destination address of JMP.
In this example, since the instruction at the return destination address is RTS,
even if RTS is used instead of JMP , the operation is the same as that of JMP .
As a result, the number of bytes is reduced.
2: BPL and BMI, as machine instructions, have no absolute addresses, but relative
addresses as branch destinations.
Fig. 5.3.3 Correction example (2)
5-16
7220 Group User’s Manual