7220 Datasheet, PDF (197/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
5.4 Example of I²C-BUS interface control (M37221Mx-XXXSP/FP)
(2) Read processing routine
Œ

Ž

Slave address ^A
S _{(W) “A016”}
C
K
Sub-address
A
C
R
KS
Read start
Initialization
S2 (address 00DB 16) ←“110001012”
S1D (address 00DA 16) _{←“010010002”}
IICE (bit6 at address 00FE 16) _{←“0”}
S1 (address 00D9 16) ←“000100002”

‘
’
A: Accumulator
S0: I²C data shift register
Slave address ^A
A
(R) “A116”
C
K
Data
CP
K
S1: I²C status register
S2: I²C clock control register
S1D: I²C control register
IICE: Multi-master I ²C interface
interrupt enable bit
BB: Bus busy flag
TRX: Communication mode
specification bit
ACK BIT: ACK bit
PIN: I²C-BUS interface interrupt
request bit
Disable multi-master I ²C-BUS interface. ^{RS: Restart condition}
Setting for outputting the START condition
in data output processing routine.
(A)←Slave address (W) “A0 16”
Data output
S1 (address 00D9 16) ←“001000002”
(A)←Slave address (R) “A1 16”
Data output
TRX (bit 6 at address 00D9 16) ^{←“0”}
ACK BIT (bit 6 at address 00DB 16) ←“0”
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Transmit the START condition, slave
address (W) , and sub-address.
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Transmit the RESTART condtion and
slave address (R).
Set to receive mode
Set ACK return mode.
Immediately before
No
the last receive byte?
Yes
ACK BIT (bit 6 at address 00DB 16)←“1”
Set to non-ACK return mode.
No
End of reception of
S0 (address 00D7 16)←“FF16”
Preparation for judging of timeout.
Timeout ? (See note 2)
‘^{Input start}
(Set dummy data to
generate clock.)
Yes
the last receive byte
Yes
After data is received, no
acknowledge bits are
generated, but the STOP
condition is sent by the
master, completing this
read operation.
No
Waiting receive end
PIN (bit 4 at address 00D9 16)≠“1”?
No (not end)
Yes (end)
Store recive data to internal RAM
Within 10
I
←“1”
machine
S1 (address 00F8 16) ←“110000002”
cycles
S1 (address 00F8 16) _{←“110100002”}
I
←“0”
’Transmit the STOP condition.
Note 1: Be sure to set between S1
and S1 within 10 machine cycles.
End
Note 2: The timeout count is performed by software with interrupts, such as timers. Accordingly, if receive
operation is not completed due to various influences, the loop continues. Therefore, if receive
operation does not complete within a certain time, I ² C-BUS access is stopped by outputting STOP
condition. If I ²C-BUS access is stopped by timeout, the obtained data is incorrect data.
Fig. 5.4.5 Flowchart of read processing routine
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7220 Group User’s Manual