7220 Datasheet, PDF (54/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.5 Interrupts
2.5.1 Interrupt sources
The following explains interrupt sources, in order of priority (except reset).
(1) CRT interrupt
When displaying a character block with the CRT display function, the CRT interrupt request occurs
at the completion of the display.
(2) INT2 interrupt
An INT2 interrupt request is generated by detecting a level transition on pin INT2 (external interrupt
input).
Detecting either positive polarity (LOW to HIGH transition) or negative polarity (HIGH to LOW transition)
is set with RE4 (the interrupt input polarity register: bit 4 at address 00F916). When RE4 is set to “0,”
a positive polarity is detected; when RE4 is set to “1,” a negative polarity is detected.
The INT2 pin is also used for port P06 and pin A-D4. An INT2 interrupt by a level transition on the
pin may cause software runaway. Therefore, when this pin is used as port P06, disable an INT2
interrupt by using an interrupt enable bit and the interrupt disable flag (I).
(3) INT1 interrupt
An INT1 interrupt request is generated by detecting a level transition on pin INT1 (external interrupt
input).
Detecting either positive polarity (LOW to HIGH transition) or negative polarity (HIGH to LOW transition)
to be detected is set with RE3 (the interrupt input polarity register: bit 3 at address 00F916). When
RE3 is set to “0,” a positive polarity is detected; when RE3 is set to “1,” a negative polarity is
detected.
Pin INT1 is also used for port P07. An INT1 interrupt by a level transition on the pin may cause
software runaway. Therefore, when this pin is used as port P07, disable the INT1 interrupt by using
an interrupt enable bit and interrupt disable flag (I).
(4) Timer 4 interrupt
Timer 4 value is counted down. Timer 4 interrupt request occurs when the count source next to “0016”
is input.
(5) f(XIN)/4096 interrupt
A f(XIN)/4096 interrupt request occurs for a f(XIN)/4096 period.
This interrupt is valid when the PWM count source is supplied (when bit 0 of PWM output control
register 1 is “0”).
(6) VSYNC interrupt
A VSYNC interrupt request occurs synchronized
with the vertical synchronous signal which
is input to pin VSYNC.
When the VSYNC input polarity is positive (the
CRT port control register: bit 1 at address
00EC16 is “0”), an interrupt request is
generated by a rising edge (LOW to HIGH
transition) of the VSYNC input; conversely,
when the polarity is negative, an interrupt
request is generated by a falling edge.
Positive polarity
input
Negative polarity
input
VSYNC
input pin
: Interrupt request is generated
Fig. 2.5.1 VSYNC interrupt generation timing
7220 Group User’s Manual
2-27