7220 Datasheet, PDF (118/303 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

FUNCTIONAL DESCRIPTION
2.14 Low-power dissipation mode
2.14 Low-power dissipation mode
The M37221M6-XXXSP/FP has 2 low-power dissipation modes: the stop mode and the wait mode.
2.14.1 Stop mode
The M37221M6-XXXSP/FP allows the oscillation of XIN to be stopped with keeping all states of registers
except timers 3 and 4, input/output ports, and internal RAM. Therefore, the M37221M6-XXXSP/FP can be
restarted with the same state where oscillation was stopped, and as a result, the power dissipation can be
greatly reduced.
To stop oscillating in such a way, execute the STP instruction. The stop mode is set by executing the STP
instruction. In this mode, the address to fetch the instruction next to the STP instruction is output to the
address bus, and the oscillation stops with HIGH state of the internal clock φ. At this time, the timer 3
overflow signal is further connected to timer 4. Value “FF16” is automatically set to timer 3; value “0716” is
automatically set to timer 4.
Immediately before executing the STP instruction, process the following sequence:
ΠStore registers (accumulator, index registers, etc.) in the CPU to internal RAM.
 Disable timers 3 and 4 interrupts (TM3E = TM4E = “0”).
Ž Clear timers 3 and 4 count stop bits to “0” (T34M2 = T34M3 = “0”).
 When an interrupt is used for return from the stop mode, enable that interrupt (by clearing the interrupt
disable flag to “0” and setting the interrupt enable bit to “1”).
 Set bit 0 of the timer 34 mode register (address 00F516) to “0” (TM34M0=“0”) to select f(XIN)/16 as the
timer 3 count source.
Oscillation is restarted (return from the stop mode) by accepting reset input or interrupt request of INT1,
INT2 or INT3. When the interrupt request is accepted, the interrupt processing routine is executed. Note,
however, that the internal clock φ is not supplied to the CPU until timer 4 overflows after the interrupt
request is accepted. This is because a finite time is required for stabilizing of oscillation when an external
quartz-crystal oscillator, etc. is used.
When the internal clock φ is supplied to the CPU, the CPU executes the interrupt routine. At this time, the
address for the first byte of the instruction next to the STP instruction is pushed to the stack as a return
address. Also note that the timers 3 and 4 interrupt request bits are remained setting to “1.” Therefore,
clear each bit to “0” in the interrupt routine. Enable one of the INT1, INT2 and INT3 interrupts to use
interrupts for restarting oscillation before the executing STP instruction (described in  above).
Table 2.14.1 State in stop mode
Item
Oscillation
CPU
Internal clock φ
I/O ports
Timer, CRT display functions
State in stop mode
Stops
Stops
Stops at HIGH level
State where STP instruction is executed is held.
Stops
7220 Group User’s Manual
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