PIC18F2480_09 Datasheet, PDF (87/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR Page:
RXB0CON
Mode 0
RXFUL
RXM1
RXM0⁽⁷⁾
—⁽⁷⁾
RXRTRRO⁽⁷⁾ RXBODBEN⁽⁷⁾ JTOFF⁽⁷⁾
FILHIT0^{(7) 000- 0000 59, 293}
RXB0CON
Mode 1, 2
RXFUL
RXM1
RTRRO FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0 0000 0000 59, 293
RXB1D7
RXB1D6
RXB1D5
RXB1D4
RXB1D3
RXB1D2
RXB1D1
RXB1D0
RXB1DLC
RXB1EIDL
RXB1EIDH
RXB1SIDL
RXB1SIDH
RXB1CON
Mode 0
RXB1D77
RXB1D67
RXB1D57
RXB1D47
RXB1D37
RXB1D27
RXB1D17
RXB1D07
—
EID7
EID15
SID2
SID10
RXFUL
RXB1D76
RXB1D66
RXB1D56
RXB1D46
RXB1D36
RXB1D26
RXB1D16
RXB1D06
RXRTR
EID6
EID14
SID1
SID9
RXM1
RXB1D75
RXB1D65
RXB1D55
RXB1D45
RXB1D35
RXB1D25
RXB1D15
RXB1D05
RB1
EID5
EID13
SID0
SID8
RXM0⁽⁷⁾
RXB1D74 RXB1D73
RXB1D64 RXB1D63
RXB1D54 RXB1D53
RXB1D44 RXB1D43
RXB1D34 RXB1D33
RXB1D24 RXB1D23
RXB1D14 RXB1D13
RXB1D04 RXB1D03
RB0
DLC3
EID4
EID3
EID12
EID11
SRR
EXID
SID7
—⁽⁷⁾
SID6
RXRTRRO⁽⁷⁾
RXB1D72
RXB1D62
RXB1D52
RXB1D42
RXB1D32
RXB1D22
RXB1D12
RXB1D02
DLC2
EID2
EID10
—
SID5
FILHIT2⁽⁷⁾
RXB1D71
RXB1D61
RXB1D51
RXB1D41
RXB1D31
RXB1D21
RXB1D11
RXB1D01
DLC1
EID1
EID9
EID17
SID4
FILHIT1⁽⁷⁾
RXB1D70
RXB1D60
RXB1D50
RXB1D40
RXB1D30
RXB1D20
RXB1D10
RXB1D00
DLC0
EID0
EID8
EID16
SID3
FILHIT0⁽⁷⁾
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
-xxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
000- 0000
59, 298
59, 298
59, 298
59, 298
59, 298
59, 298
59, 298
59, 298
59, 298
59, 297
59, 297
59, 297
60, 296
60, 293
RXB1CON
Mode 1, 2
RXFUL
RXM1
RTRRO FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0 0000 0000 60, 293
TXB0D7
TXB0D77 TXB0D76 TXB0D75 TXB0D74 TXB0D73
TXB0D72
TXB0D71 TXB0D70 xxxx xxxx 60, 290
TXB0D6
TXB0D67 TXB0D66 TXB0D65 TXB0D64 TXB0D63
TXB0D62
TXB0D61 TXB0D60 xxxx xxxx 60, 290
TXB0D5
TXB0D57 TXB0D56 TXB0D55 TXB0D54 TXB0D53
TXB0D52
TXB0D51 TXB0D50 xxxx xxxx 60, 290
TXB0D4
TXB0D47 TXB0D46 TXB0D45 TXB0D44 TXB0D43
TXB0D42
TXB0D41 TXB0D40 xxxx xxxx 60, 290
TXB0D3
TXB0D37 TXB0D36 TXB0D35 TXB0D34 TXB0D33
TXB0D32
TXB0D31 TXB0D30 xxxx xxxx 60, 290
TXB0D2
TXB0D27 TXB0D26 TXB0D25 TXB0D24 TXB0D23
TXB0D22
TXB0D21 TXB0D20 xxxx xxxx 60, 290
TXB0D1
TXB0D17 TXB0D16 TXB0D15 TXB0D14 TXB0D13
TXB0D12
TXB0D11
TXB0D10 xxxx xxxx 60, 290
TXB0D0
TXB0D07 TXB0D06 TXB0D05 TXB0D04 TXB0D03
TXB0D02
TXB0D01 TXB0D00 xxxx xxxx 60, 290
TXB0DLC
—
TXRTR
—
—
DLC3
DLC2
DLC1
DLC0 -x-- xxxx 60, 291
TXB0EIDL
EID7
EID6
EID5
EID4
EID3
EID2
EID1
EID0
xxxx xxxx 60, 290
TXB0EIDH
EID15
EID14
EID13
EID12
EID11
EID10
EID9
EID8
xxxx xxxx 60, 289
TXB0SIDL
SID2
SID1
SID0
—
EXIDE
—
EID17
EID16 xxx- x-xx 60, 289
TXB0SIDH
SID10
SID9
SID8
SID7
SID6
SID5
SID4
SID3
xxxx xxxx 60, 289
TXB0CON
TXBIF
TXABT TXLARB TXERR
TXREQ
—
TXPRI1
TXPRI0 0000 0-00 60, 288
TXB1D7
TXB1D77 TXB1D76 TXB1D75 TXB1D74 TXB1D73
TXB1D72
TXB1D71 TXB1D70 xxxx xxxx 60, 290
TXB1D6
TXB1D67 TXB1D66 TXB1D65 TXB1D64 TXB1D63
TXB1D62
TXB1D61 TXB1D60 xxxx xxxx 60, 290
TXB1D5
TXB1D57 TXB1D56 TXB1D55 TXB1D54 TXB1D53
TXB1D52
TXB1D51 TXB1D50 xxxx xxxx 60, 290
TXB1D4
TXB1D47 TXB1D46 TXB1D45 TXB1D44 TXB1D43
TXB1D42
TXB1D41 TXB1D40 xxxx xxxx 60, 290
TXB1D3
TXB1D37 TXB1D36 TXB1D35 TXB1D34 TXB1D33
TXB1D32
TXB1D31 TXB1D30 xxxx xxxx 60, 290
TXB1D2
TXB1D27 TXB1D26 TXB1D25 TXB1D24 TXB1D23
TXB1D22
TXB1D21 TXB1D20 xxxx xxxx 60, 290
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 87