PIC18F2480_09 Datasheet, PDF (364/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L —
—
—
—
CP3*
300009h CONFIG5H CPD
CPB
—
—
—
30000Ah CONFIG6L —
—
—
—
WRT3*
30000Bh CONFIG6H WRTD WRTB WRTC
—
—
30000Ch CONFIG7L —
—
—
—
EBTR3*
30000Dh CONFIG7H —
EBTRB
—
—
—
Legend: Shaded cells are unimplemented.
* Unimplemented in PIC18FX480 devices; maintain this bit set.
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
25.5.1 PROGRAM MEMORY
CODE PROTECTION
The program memory may be read to or written from
any location using the table read and table write
instructions. The Device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A
block of user memory may be protected from table
writes if the WRTn Configuration bit is ‘0’. The EBTRn
bits control table reads. For a block of user memory
with the EBTRn bit set to ‘0’, a table read instruction
that executes from within that block is allowed to read.
A table read instruction that executes from a location
outside of that block is not allowed to read and will
result in reading ‘0’s. Figures 25-6 through 25-8
illustrate table write and table read protection.
Note:
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
FIGURE 25-6:
TABLE WRITE (WRTn) DISALLOWED
Register Values
TBLPTR = 0008FFh
Program Memory
000000h
0007FFh
000800h
PC = 003FFEh
PC = 00BFFEh
TBLWT*
TBLWT*
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Results: All table writes disabled to Blockn whenever WRTn = 0.
Configuration Bit Settings
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
DS39637D-page 364
© 2009 Microchip Technology Inc.