PIC18F2480_09 Datasheet, PDF (85/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR Page:
SPBRGH
EUSART Baud Rate Generator High Byte
0000 0000 57, 236
SPBRG
EUSART Baud Rate Generator
0000 0000 57, 236
RCREG
EUSART Receive Register
0000 0000 57, 244
TXREG
EUSART Transmit Register
0000 0000 57, 241
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 57, 243
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 57, 243
EEADR
EEPROM Address Register
0000 0000 57, 111
EEDATA
EEPROM Data Register
0000 0000 57, 111
EECON2
EEPROM Control Register 2 (not a physical register)
0000 0000 57, 111
EECON1
EEPGD
CFGS
—
FREE
WRERR
WREN
WR
RD
xx-0 x000 57, 111
IPR3
Mode 0
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP 1111 1111 57, 132
IPR3
Mode 1, 2
IRXIP
WAKIP
ERRIP
TXBnIP
TXB1IP⁽⁸⁾
TXB0IP⁽⁸⁾
RXBnIP FIFOWMIP 1111 1111 57, 132
PIR3
Mode 0
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF 0000 0000 57, 126
PIR3
Mode 1, 2
IRXIF
WAKIF
ERRIF
TXBnIF
TXB1IF⁽⁸⁾
TXB0IF⁽⁸⁾
RXBnIF FIFOWMIF 0000 0000 57, 126
PIE3
Mode 0
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE 0000 0000 57, 129
PIE3
Mode 1, 2
IPR2
PIR2
PIE2
IPR1
PIR1
PIE1
OSCTUNE
TRISE⁽³⁾
TRISD⁽³⁾
IRXIE
WAKIE
ERRIE
TXBnIE _TXB1IE(8)
OSCFIP
OSCFIF
OSCFIE
PSPIP⁽³⁾
PSPIF⁽³⁾
PSPIE⁽³⁾
INTSRC
CMIP⁽⁹⁾
CMIF⁽⁹⁾
CMIE⁽⁹⁾
ADIP
ADIF
ADIE
PLLEN⁽⁴⁾
—
—
—
RCIP
RCIF
RCIE
—
IBF
OBF
IBOV
PORTD Data Direction Register
EEIP
EEIF
EEIE
TXIP
TXIF
TXIE
TUN4
PSPMODE
BCLIP
BCLIF
BCLIE
SSPIP
SSPIF
SSPIE
TUN3
—
TXB0IE⁽⁸⁾
HLVDIP
HLVDIF
HLVDIE
CCP1IP
CCP1IF
CCP1IE
TUN2
TRISE2
RXBnIE
TMR3IP
TMR3IF
TMR3IE
TMR2IP
TMR2IF
TMR2IE
TUN1
TRISE1
FIFOMWIE 0000 0000 57, 129
ECCP1IP⁽⁹⁾
ECCP1IF⁽⁹⁾
ECCP1IE⁽⁹⁾
TMR1IP
TMR1IF
TMR1IE
TUN0
TRISE0
11-1 1111
00-0 0000
00-0 0000
1111 1111
0000 0000
0000 0000
0q-0 0000
0000 -111
1111 1111
57, 131
58, 125
58, 128
58, 130
58, 124
58, 127
33, 58
58, 146
58, 143
TRISC
PORTC Data Direction Register
1111 1111 58, 141
TRISB
TRISA
LATE⁽³⁾
LATD⁽³⁾
PORTB Data Direction Register
TRISA7⁽⁶⁾ TRISA6⁽⁶⁾ PORTA Data Direction Register
—
—
—
—
—
LATD Output Latch Register
LATE2
LATE1
LATE0
1111 1111
1111 1111
---- -xxx
xxxx xxxx
58, 138
58, 135
58, 146
58, 143
LATC
LATC Output Latch Register
xxxx xxxx 58, 141
LATB
LATA
LATB Output Latch Register
LATA7⁽⁶⁾
LATA6⁽⁶⁾ LATA Output Latch Register
xxxx xxxx 58, 138
xxxx xxxx 58, 135
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 85