PIC18F2480_09 Datasheet, PDF (483/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
STATUS ..................................................................... 94
STKPTR (Stack Pointer) ............................................ 69
T0CON (Timer0 Control) .......................................... 151
T1CON (Timer 1 Control) ......................................... 155
T2CON (Timer2 Control) .......................................... 161
T3CON (Timer3 Control) .......................................... 163
TRISE (PORTE/PSP Control) .................................. 147
TXBIE (Transmit Buffers Interrupt Enable) .............. 324
TXBnCON (Transmit Buffer n Control) .................... 288
TXBnDLC (Transmit Buffer n
Data Length Code) .......................................... 291
TXBnDm (Transmit Buffer n Data Field Byte m) ...... 290
TXBnEIDH (Transmit Buffer n Extended
Identifier, High Byte) ........................................ 289
TXBnEIDL (Transmit Buffer n Extended
Identifier, Low Byte) ......................................... 290
TXBnSIDH (Transmit Buffer n Standard
Identifier, High Byte) ........................................ 289
TXBnSIDL (Transmit Buffer n Standard
Identifier, Low Byte) ......................................... 289
TXERRCNT (Transmit Error Count) ........................ 291
TXSTA (Transmit Status and Control) ..................... 232
WDTCON (Watchdog Timer Control) ...................... 359
RESET ............................................................................. 397
Resets ........................................................................ 47, 349
Brown-out Reset (BOR) ........................................... 349
Oscillator Start-up Timer (OST) ............................... 349
Power-on Reset (POR) ............................................ 349
Power-up Timer (PWRT) ......................................... 349
RETFIE ............................................................................ 398
RETLW ............................................................................ 398
RETURN .......................................................................... 399
Return Address Stack ........................................................ 68
and Associated Registers .......................................... 68
Return Stack Pointer (STKPTR) ........................................ 69
Revision History ............................................................... 471
RLCF ................................................................................ 399
RLNCF ............................................................................. 400
RRCF ............................................................................... 400
RRNCF ............................................................................ 401
S
SCK .................................................................................. 191
SDI ................................................................................... 191
SDO ................................................................................. 191
SEC_IDLE Mode ................................................................ 44
SEC_RUN Mode ................................................................ 40
Serial Clock, SCK ............................................................ 191
Serial Data In (SDI) .......................................................... 191
Serial Data Out (SDO) ..................................................... 191
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 401
Slave Select (SS) ............................................................. 191
SLEEP ............................................................................. 402
Sleep
OSC1 and OSC2 Pin States ...................................... 37
Software Simulator (MPLAB SIM) .................................... 419
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 349
Special Function Registers ................................................ 77
Map ...................................................................... 77–82
SPI Mode (MSSP)
Associated Registers ............................................... 199
Bus Mode Compatibility ........................................... 199
Effects of a Reset ..................................................... 199
© 2009 Microchip Technology Inc.
Enabling SPI I/O ...................................................... 195
Master Mode ............................................................ 196
Master/Slave Connection ........................................ 195
Operation ................................................................. 194
Operation in Power-Managed Modes ...................... 199
Serial Clock ............................................................. 191
Serial Data In ........................................................... 191
Serial Data Out ........................................................ 191
Slave Mode .............................................................. 197
Slave Select ............................................................. 191
Slave Select Synchronization .................................. 197
SPI Clock ................................................................. 196
Typical Connection .................................................. 195
SS .................................................................................... 191
SSPOV ............................................................................ 221
SSPOV Status Flag ......................................................... 221
SSPSTAT Register
R/W Bit ............................................................ 204, 205
Stack Full/Underflow Resets .............................................. 70
STATUS Register .............................................................. 94
SUBFSR .......................................................................... 413
SUBFWB ......................................................................... 402
SUBLW ............................................................................ 403
SUBULNK ........................................................................ 413
SUBWF ............................................................................ 403
SUBWFB ......................................................................... 404
SWAPF ............................................................................ 404
T
T0CON Register
PSA Bit .................................................................... 153
T0CS Bit .................................................................. 152
T0PS2:T0PS0 Bits ................................................... 153
T0SE Bit .................................................................. 152
Table Pointer Operations (table) ...................................... 104
Table Reads/Table Writes ................................................. 70
TBLRD ............................................................................. 405
TBLWT ............................................................................ 406
Time-out in Various Situations (table) ................................ 51
Timer0 ............................................................................. 151
16-Bit Mode Reads and Writes ................................ 152
Associated Registers ............................................... 153
Clock Source Edge Select (T0SE Bit) ..................... 152
Clock Source Select (T0CS Bit) .............................. 152
Operation ................................................................. 152
Overflow Interrupt .................................................... 153
Prescaler. See Prescaler, Timer0.
Timer1 ............................................................................. 155
16-Bit Read/Write Mode .......................................... 157
Associated Registers ............................................... 159
Interrupt ................................................................... 158
Operation ................................................................. 156
Oscillator .......................................................... 155, 157
Oscillator Layout Considerations ............................. 158
Overflow Interrupt .................................................... 155
Resetting, Using a Special Event Trigger
Output (CCP) .................................................. 158
Special Event Trigger (ECCP) ................................. 178
TMR1H Register ...................................................... 155
TMR1L Register ...................................................... 155
Use as a Real-Time Clock ....................................... 158
Timer2 ............................................................................. 161
Associated Registers ............................................... 162
Interrupt ................................................................... 162
Operation ................................................................. 161
Output ...................................................................... 162
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