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PIC18F2480_09 Datasheet, PDF (58/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
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PIC18F2480/2580/4480/4580
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
PIR2
PIE2
IPR1
PIR1
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
00-0 0000
0--0 000-
00-0 0000
0--0 000-
1111 1111
-111 1111
0000 0000
00-0 0000
0--0 000-
00-0 0000
0--0 000-
1111 1111
-111 1111
0000 0000
uu-u uuuu(1)
u--u uuu-(1)
uu-u uuuu
u--u uuu-
uuuu uuuu
-uuu uuuu
uuuu uuuu(1)
2480 2580 4480 4580 -000 0000
-000 0000
-uuu uuuu
PIE1
OSCTUNE
TRISE
TRISD
TRISC
TRISB
TRISA(5)
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
0000 0000
-000 0000
--00 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111(5)
0000 0000
-000 0000
--00 0000
0000 -111
1111 1111
1111 1111
1111 1111
1111 1111(5)
uuuu uuuu
-uuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
LATE
2480 2580 4480 4580 ---- -xxx
---- -uuu
---- -uuu
LATD
LATC
LATB
LATA(5)
PORTE
PORTD
PORTC
PORTB
PORTA(5)
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx(5)
---- x000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- x000
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu0u 0000(5)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu(5)
ECANCON 2480 2580 4480 4580 0001 0000
0001 0000
uuuu uuuu
TXERRCNT 2480 2580 4480 4580 0000 0000
0000 0000
uuuu uuuu
RXERRCNT 2480 2580 4480 4580 0000 0000
0000 0000
uuuu uuuu
COMSTAT
2480 2580 4480 4580
0000 0000
0000 0000
uuuu uuuu
CIOCON
2480 2580 4480 4580 --00 ----
--00 ----
--uu ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.
DS39637D-page 58
© 2009 Microchip Technology Inc.
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