PIC18F2480_09 Datasheet, PDF (363/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
25.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 16 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
FIGURE 25-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F2480/2580/4480/4580
Address
Range
BBSIZ
000000h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
MEMORY SIZE/DEVICE
32 Kbytes
(PIC18F2580/4580)
16 Kbytes
(PIC18F2480/4480)
0
1
0
1
Boot Block
1 kW
Boot Block
2 kW
Boot Block
1 kW
Boot Block
2 kW
Block 0
3 kW
Block 0
2 kW
Block 0
3 kW
Block 0
2 kW
Block 1
4 kW
Block 1
4 kW
Block 1
4 kW
Block 1
4 kW
Block 2
4 kW
Block 2
4 kW
Block 3
4 kW
Block 3
4 kW
Block Code Protection
Controlled by:
CPB, WRTB, EBRTB
(Boot Block)
CP0, WRT0, EBRT0
(Block 0)
CP!, WRT1, EBRT1
(Block 1)
CP2, WRT2, EBRT2
(Block 2)
CP3, WRT3, EBTR3
(Block 3)
Unimplemented Unimplemented
Read ‘0’s
Read ‘0’s
Unimplemented Unimplemented
Read ‘0’s
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
© 2009 Microchip Technology Inc.
DS39637D-page 363