PIC18F2480_09 Datasheet, PDF (71/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
6.2 PIC18 Instruction Cycle
6.2.1 CLOCKING SCHEME
The microcontroller clock input, whether from an inter-
nal or external source, is internally divided by four to
generate four non-overlapping quadrature clocks (Q1,
Q2, Q3 and Q4). Internally, the Program Counter (PC)
is incremented on every Q1; the instruction is fetched
from the program memory and latched into the Instruc-
tion Register (IR) during Q4. The instruction is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow are shown in
Figure 6-3.
6.2.2 INSTRUCTION FLOW/PIPELINING
An “Instruction Cycle” consists of four Q cycles: Q1
through Q4. The instruction fetch and execute are
pipelined in such a manner that a fetch takes one
instruction cycle, while the decode and execute take
another instruction cycle. However, due to the
pipelining, each instruction effectively executes in one
cycle. If an instruction causes the program counter to
change (e.g., GOTO), then two cycles are required to
complete the instruction (Example 6-3).
A fetch cycle begins with the program counter
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 6-3:
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKO
(RC mode)
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Execute INST (PC – 2)
Fetch INST (PC)
PC + 2
Execute INST (PC)
Fetch INST (PC + 2)
Q1 Q2 Q3 Q4
PC + 4
Execute INST (PC + 2)
Fetch INST (PC + 4)
Internal
Phase
Clock
EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW
TCY0
TCY1
1. MOVLW 55h
Fetch 1 Execute 1
2. MOVWF PORTB
Fetch 2
3. BRA SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
TCY2
Execute 2
Fetch 3
TCY3
TCY4
TCY5
Execute 3
Fetch 4 Flush (NOP)
Fetch SUB_1 Execute SUB_1
Note:
All instructions are single cycle, except for any program branches. These take two cycles since the
fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then
executed.
© 2009 Microchip Technology Inc.
DS39637D-page 71