PIC18F2480_09 Datasheet, PDF (288/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
24.2.2 DEDICATED CAN TRANSMIT
BUFFER REGISTERS
This section describes the dedicated CAN Transmit
Buffer registers and their associated control registers.
REGISTER 24-5: TXBnCON: TRANSMIT BUFFER n CONTROL REGISTERS [0 ≤ n ≤ 2]
Mode 0
U-0
R-0
R-0
R-0
R/W-0
U-0
R/W-0
R/W-0
—
TXABT⁽¹⁾ TXLARB⁽¹⁾ TXERR⁽¹⁾ TXREQ⁽²⁾
—
TXPRI1⁽³⁾ TXPRI0⁽³⁾
Mode 1,2
R/C-0
TXBIF
bit 7
R-0
R-0
R-0
R/W-0
U-0
TXABT⁽¹⁾ TXLARB⁽¹⁾ TXERR⁽¹⁾ TXREQ⁽²⁾
—
R/W-0
TXPRI1⁽³⁾
R/W-0
TXPRI0⁽³⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
Mode 0:
Unimplemented: Read as ‘0’
Mode 1, 2:
TXBIF: Transmit Buffer Interrupt Flag bit
1 = Transmit buffer has completed transmission of message and may be reloaded
0 = Transmit buffer has not completed transmission of a message
TXABT: Transmission Aborted Status bit⁽¹⁾
1 = Message was aborted
0 = Message was not aborted
TXLARB: Transmission Lost Arbitration Status bit⁽¹⁾
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
TXERR: Transmission Error Detected Status bit⁽¹⁾
1 = A bus error occurred while the message was being sent
0 = A bus error did not occur while the message was being sent
TXREQ: Transmit Request Status bit⁽²⁾
1 = Requests sending a message. Clears the TXABT, TXLARB and TXERR bits.
0 = Automatically cleared when the message is successfully sent
Unimplemented: Read as ‘0’
TXPRI<1:0>: Transmit Priority bits⁽³⁾
11 = Priority Level 3 (highest priority)
10 = Priority Level 2
01 = Priority Level 1
00 = Priority Level 0 (lowest priority)
Note 1:
2:
3:
This bit is automatically cleared when TXREQ is set.
While TXREQ is set, Transmit Buffer registers remain read-only. Clearing this bit in software while the bit is
set will request a message abort.
These bits define the order in which transmit buffers will be transferred. They do not alter the CAN
message identifier.
DS39637D-page 288
© 2009 Microchip Technology Inc.