PIC18F2480_09 Datasheet, PDF (148/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 11-9: PORTE I/O SUMMARY
Pin Name
Function I/O TRIS Buffer
Description
RE0/RD/AN5
RE0 OUT 0
IN 1
DIG LATE<0> data output.
ST PORTE<0> data input.
RD
IN 1 TTL PSP read enable input.
AN5 IN 1 ANA A/D Input Channel 5. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
RE1/WR/AN6/C1OUT
RE1 OUT 0
IN 1
DIG LATE<1> data output.
ST PORTE<1> data input.
WR
IN 1 TTL PSP write enable input.
AN6 IN 1 ANA A/D Input Channel 6. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
C1OUT OUT 0 DIG Comparator 1 output.
RE2/CS/AN7/C2OUT
RE2 OUT 0
IN 1
DIG LATE<2> data output.
ST PORTE<2> data input.
CS
IN 1 TTL PSP chip select input.
AN7 IN 1 ANA A/D Input Channel 7. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
C2OUT OUT 0 DIG Comparator 2 output.
MCLR/VPP/RE3
MCLR IN x ST External Reset input. Disabled when MCLRE Configuration bit is ‘1’.
VPP
IN x ANA High-voltage detection; used by ICSP™ operation.
RE3 IN 1 ST PORTE<3> data input. Disabled when MCLRE Configuration bit is ‘0’.
Legend: PWR = Power Supply, OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
PORTE⁽³⁾
—
LATE⁽²⁾
—
TRISE⁽³⁾
IBF
—
—
OBF
—
—
RE3^(1,2)
RE2
RE1
RE0
58
—
—
— LATE Output Latch Register
58
IBOV PSPMODE —
TRISE2 TRISE1 TRISE0
58
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
56
CMCON⁽³⁾ C2OUT C1OUT C2INV
C1INV
CIS
CM2
CM1
CM0
57
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both PIC18F2X80 and PIC18F4X80 devices. All other bits are
implemented only when PORTE is implemented (i.e., PIC18F4X80 devices).
3: These registers are unimplemented on PIC18F2X80 devices.
DS39637D-page 148
© 2009 Microchip Technology Inc.