PIC18F2480_09 Datasheet, PDF (83/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 6-2: REGISTER FILE SUMMARY (PIC18F2480/2580/4480/4580)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details on
POR, BOR Page:
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 55, 68
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 55, 68
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 55, 68
STKPTR
PCLATU
STKFUL
—
STKUNF
—
—
Return Stack Pointer
bit 21⁽¹⁾ Holding Register for PC<20:16>
00-0 0000 55, 69
---0 0000 55, 68
PCLATH
Holding Register for PC<15:8>
0000 0000 55, 68
PCL
PC Low Byte (PC<7:0>)
0000 0000 55, 68
TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000 55, 109
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 55, 109
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 55, 109
TABLAT
Program Memory Table Latch
0000 0000 55, 109
PRODH
Product Register High Byte
xxxx xxxx 55, 117
PRODL
Product Register Low Byte
xxxx xxxx 55, 117
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 55, 121
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 55, 122
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 55, 123
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
55, 96
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
55, 97
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
55, 97
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
55, 97
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register), value of
FSR0 offset by W
N/A
55, 97
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
---- xxxx 55, 96
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 55, 96
WREG
Working Register
xxxx xxxx 55
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
55, 96
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
55, 97
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
55, 97
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
55, 97
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register), value of
FSR1 offset by W
N/A
55, 97
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High
---- xxxx 55, 96
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 55, 96
BSR
—
—
—
—
Bank Select Register
---- 0000 56, 73
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
56, 96
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
56, 97
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
56, 97
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
56, 97
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register), value of
FSR2 offset by W
N/A
56, 97
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
Note 1: Bit 21 of the PC is only available in Test mode and Serial Programming modes.
2: The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See Section 5.4 “Brown-out Reset (BOR)”.
3: These registers and/or bits are not implemented on PIC18F2X80 devices and are read as ‘0’. Reset values are shown for PIC18F4X80 devices;
individual unimplemented bits should be interpreted as ‘—’.
4: The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as ‘0’. See Section 3.6.4 “PLL in INTOSC
Modes”.
5: The RE3 bit is only available when Master Clear Reset is disabled (CONFIG3H<7> = 0); otherwise, RE3 reads as ‘0’. This bit is read-only.
6: RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When
disabled, these bits read as ‘0’.
7: CAN bits have multiple functions depending on the selected mode of the CAN module.
8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.
9: These registers are available on PIC18F4X80 devices only.
© 2009 Microchip Technology Inc.
DS39637D-page 83