PIC18F2480_09 Datasheet, PDF (217/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
18.4.7 BAUD RATE
In I²C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 18-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I²C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 18-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 18-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<6:0>
SSPM<3:0>
SCL
Reload
Control
Reload
CLKO
BRG Down Counter
FOSC/4
TABLE 18-3: I²C™ CLOCK RATE W/BRG
FCY
FCY*2
10 MHz
10 MHz
10 MHz
4 MHz
4 MHz
4 MHz
1 MHz
1 MHz
20 MHz
20 MHz
20 MHz
8 MHz
8 MHz
8 MHz
2 MHz
2 MHz
BRG Value
19h
20h
64h
0Ah
0Dh
28h
03h
0Ah
FSCL
(2 Rollovers of BRG)
400 kHz
312.5 kHz
100 kHz
400 kHz
308 kHz
100 kHz
333 kHz
100 kHz
© 2009 Microchip Technology Inc.
DS39637D-page 217