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PIC18F2480_09 Datasheet, PDF (55/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
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PIC18F2480/2580/4480/4580
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
TOSU
TOSH
TOSL
STKPTR
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 uuuu(3)
uuuu uuuu(3)
uuuu uuuu(3)
uu-u uuuu(3)
PCLATU
2480 2580 4480 4580 ---0 0000
---0 0000
---u uuuu
PCLATH
PCL
2480 2580 4480 4580
2480 2580 4480 4580
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
PC + 2(2)
TBLPTRU
2480 2580 4480 4580 --00 0000
--00 0000
--uu uuuu
TBLPTRH
2480 2580 4480 4580 0000 0000
0000 0000
uuuu uuuu
TBLPTRL
2480 2580 4480 4580 0000 0000
0000 0000
uuuu uuuu
TABLAT
2480 2580 4480 4580 0000 0000
0000 0000
uuuu uuuu
PRODH
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
PRODL
INTCON
INTCON2
INTCON3
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
2480 2580 4480 4580
xxxx xxxx
0000 000x
1111 -1-1
11-0 0-00
uuuu uuuu
0000 000u
1111 -1-1
11-0 0-00
uuuu uuuu
uuuu uuuu(1)
uuuu -u-u(1)
uu-u u-uu(1)
INDF0
2480 2580 4480 4580
N/A
N/A
N/A
POSTINC0 2480 2580 4480 4580
N/A
N/A
N/A
POSTDEC0 2480 2580 4480 4580
N/A
N/A
N/A
PREINC0
2480 2580 4480 4580
N/A
N/A
N/A
PLUSW0
2480 2580 4480 4580
N/A
N/A
N/A
FSR0H
2480 2580 4480 4580 ---- 0000
---- 0000
---- uuuu
FSR0L
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
WREG
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF1
2480 2580 4480 4580
N/A
N/A
N/A
POSTINC1 2480 2580 4480 4580
N/A
N/A
N/A
POSTDEC1 2480 2580 4480 4580
N/A
N/A
N/A
PREINC1
2480 2580 4480 4580
N/A
N/A
N/A
PLUSW1
2480 2580 4480 4580
N/A
N/A
N/A
FSR1H
2480 2580 4480 4580 ---- 0000
---- 0000
---- uuuu
FSR1L
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.
© 2009 Microchip Technology Inc.
DS39637D-page 55
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