PIC18F2480_09 Datasheet, PDF (450/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
FIGURE 28-15:
SS
EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SCK
(CKP = 0)
70
71
72
SCK
(CKP = 1)
80
SDO
SDI
MSb
bit 6 - - - - - -1
75, 76
MSb In
bit 6 - - - -1
74
LSb
LSb In
83
77
TABLE 28-17: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TSSL2SCH, SS ↓ to SCK ↓ or SCK ↑ Input
TSSL2SCL
3 TCY
—
71
TSCH
SCK Input High Time
Continuous
1.25 TCY + 30 —
71A
Single Byte
40
—
72
TSCL
SCK Input Low Time
Continuous
1.25 TCY + 30 —
72A
Single Byte
40
—
73A TB2B
Last Clock Edge of Byte 1 to the fIrst Clock Edge of Byte 2 1.5 TCY + 40 —
74 TSCH2DIL, Hold Time of SDI Data Input to SCK Edge
TSCL2DIL
40
—
75
TDOR
SDO Data Output Rise Time
PIC18FXXXX
—
25
PIC18LFXXXX
45
76
TDOF
SDO Data Output Fall Time
—
25
77 TSSH2DOZ SS↑ to SDO Output High-Impedance
10
50
80 TSCH2DOV, SDO Data Output Valid after SCK PIC18FXXXX
TSCL2DOV Edge
PIC18LFXXXX
—
50
—
100
82 TSSL2DOV SDO Data Output Valid after SS ↓ PIC18FXXXX
Edge
PIC18LFXXXX
—
50
—
100
83
TSCH2SSH, SS ↑ after SCK Edge
TSCL2SSH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns VDD = 2.0V
ns
DS39637D-page 450
© 2009 Microchip Technology Inc.